The development of high density packaging and circuitry has led to many innovations in the design of integrated circuit packaging. The most common package, the dual in-line package, is well known for lost cost, high reliability, the standardized profile. However, it is also well known for poor packaging density, both laterally and in the vertical direction. Numerous attempts to solve packaging density problems have led to the development of the leadless ceramic chip carrier.
There are many embodiments of the leadless ceramic chip carrier, one of which is the single layer alumina carrier. In this version, alumina ceramic is formed into a substrate with circuitry and interconnecting plated through holes, vias, or castellations. The integrated circuit is then attached to the substrate and wire bonded to the substrate to provide the electrical connections. A cover is placed over the integrated circuit and attached to the substrate using an adhesive to bond the cover to the substrate.
Although this device provides much higher packaging density than the dual in-line package, there arise other functional limitations which need to be overcome in order to provide optimum packaging density and reduced vertical height.
During the manufacture of the alumina substrate, a certain amount of camber or warpage is introduced into the substrate This amount is variable, and cannot be eliminated, even with the most rigorous processing conditions. Excessive camber presents difficulties in wirebonding to the substrate and attachment of the cover to the chip carrier. It follows that these operations would be more successful and reliable if camber or warpage of the substrate were eliminated.
An automatic machine, known as a wirebonder, attaches one end of a very fine gold or aluminum wire to the integrated circuit, and the other end to the substrate, thereby making the electrical connection between the integrated circuit and the substrate. Most wirebonders do not have sophisticated sensing circuitry to sense the vertical location of the substrate, and hence cannot compensate for variations in the level of the substrate surface. When the substrate is warped, the wirebonder will not make a proper bond, because the height of the substrate varies from the programmed location. Attempts to provide the "perfect" substrate have not met with success, and premium substrates are currently supplied by expensive sorting and measuring techniques. This leads to lower yield in the manufacture of substrates, which in turn leads to higher cost substrates.
Another problem with alumina substrates lies in the process for producing the circuitry on the substrate. Industry practice is to screen print a metal-filled ink onto the substrate prior to final substrate firing, and then to co-fire the ceramic and the ink to produce a monolithic unit. During this process, a great deal of shrinkage of the alumina occurs, which is not uniform. To compensate for some of this shrinkage, the tolerance and size of the plated through holes is increased. This restricts the amount of circuitry that can be placed in a given package size. Inherent in the screen printing process is a size limitation on the lines and spaces that can be printed. Typically, 0.008 inch is the smallest line that can be reliably made with the co-fired process, and 0.018 inch is the smallest hole diameter.
Another limitation with single layer alumina assemblies is the thickness of the alumina substrate. Typical substrate thicknesses of 0.025 inch are used, in order to compromise between minimum thickness and maximum durability during assembly of the assembly. If thinner substrates are used, the breakage increases correspondingly, reducing the yield of the finished assembly. Although substrates as thin as 0.010 inches have been used, the cost to manufacture the substrates and the yield loss in assembly of the chip assembly is such that only the most exotic and expensive circuits warrant this treatment.
Excessive camber and warpage also leads to problems in the attachment of the covers. If the substrate is not flat, the cover will not seal properly, resulting in a leaking package. This is not acceptable, since the purpose of the cover is to exclude environmental contamination, and an improper seal will not perform that function. Poor sealing of covers results in yield loss during assembly of the chip assembly, again increasing the final cost of the package.
Integrated circuit packages have been made using thin laminates of glass reinforced epoxy substrates, but while accruing the advantage of a thinner substrate, this method results in a substrate that is even more warped than when using alumina. The lower flexural modulus of this substrate produces warped assemblies, creating problems when soldering and attaching the package to the main circuit board. One method of dealing with excessive warpage of the finished package is to place leads on the perimeter of the package, thereby allowing the leads to compensate for warpage or camber. This practice is most readily seen in packages using tape automated bonding, but carries several disadvantages: increased package cost, increased manufacturing cost, and increased package size.
Clearly, a need exists to provide a lower cost, lower profile, higher reliability, higher density chip assembly package.